https://github.com/aofarmakis/nibbling-bits

Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
https://github.com/aofarmakis/nibbling-bits

assembler assembly computer-architecture computer-organization hardware-description-language instruction-set-architecture processor-design single-cycle-processor verilog

Last synced: about 1 month ago
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Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.

• Host: GitHub
• URL: https://github.com/aofarmakis/nibbling-bits
• Owner: aofarmakis
• License: mit
• Created: 2024-11-30T19:56:04.000Z (6 months ago)
• Default Branch: main
• Last Pushed: 2024-12-07T16:54:10.000Z (5 months ago)
• Last Synced: 2025-04-10T04:14:53.952Z (about 1 month ago)
• Topics: assembler, assembly, computer-architecture, computer-organization, hardware-description-language, instruction-set-architecture, processor-design, single-cycle-processor, verilog
• Language: Verilog
• Homepage:
• Size: 4.01 MB
• Stars: 32
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# NibbleBuddy

This repository contains the design and documentation for a very simple 4-bit processor named NibbleBuddy. It's an educational tool meant to show how one defines an Instruction Set Architecture (ISA), builds it using discrete gates and MSI components (multiplexers, flip-flops etc), examines N-operand machines and develops a rudimentary ecosystem for said processor, that being an HDL-based design and an assembler to transform Assembly code into machine code.

## Processor diagram

![NibbleBuddy's Architecture Diagram](Images/CPU%20all.png)

*Figure 1: NibbleBuddy's Architecture Diagram.*

## Instructions

NibbleBuddy supports immediate and direct addressing modes wherever applicable, and is an accumulator-based architecture. The instructions supported are as follows:

- HALT

- STA

- LDA

- ADC

- NOR

- SETC

- JNZ

- JNC

- JMP

## Memory

NibbleBuddy is a 4-bit Harvard memory architecture processor with a 5-bit program counter and a 4-bit data memory address bus. Thus, it is limited to 32 instructions at most and 16 4-bit data memory addresses.