https://github.com/artecs-group/bench5
Simulation helper for cache microarchitectural exploration
https://github.com/artecs-group/bench5
Last synced: 3 months ago
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Simulation helper for cache microarchitectural exploration
- Host: GitHub
- URL: https://github.com/artecs-group/bench5
- Owner: artecs-group
- License: mit
- Created: 2023-03-22T16:34:18.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2024-04-10T18:06:32.000Z (about 1 year ago)
- Last Synced: 2024-04-10T21:49:11.664Z (about 1 year ago)
- Language: Python
- Size: 63.5 KB
- Stars: 1
- Watchers: 5
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.md
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README
# bench5
A tool to automatically prepare, spawn and manage simulations for cache microarchitectural exploration.
Created to work in conjunction with [gem5-artecs](https://github.com/artecs-group/gem5-artecs).
The following benchmark suites are currently supported:
* [SPEC CPU2006](https://www.spec.org/cpu2006/)
* [SPEC CPU2017](https://www.spec.org/cpu2017/)
The following operations are currently supported:
* Benchmarks simulation (SE mode)
* `-f` : Standard execution
* `-x` : From [SimPoint](https://cseweb.ucsd.edu/~calder/simpoint/)-based checkpoint
* `-r` : From [Elastic Trace](https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU)
* `-b` : Basic Block Vectors (BBV) generation
* using gem5 or [Valgrind](https://valgrind.org/docs/manual/bbv-manual.html)
* `-s` : Simulation Points extraction
* using [SimPoint](https://cseweb.ucsd.edu/~calder/simpoint/)
* `-c` : Checkpoints creation from Simulation Points
* `-t` : [Elastic Traces](https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU) generation
## Requirements ##
This script is compatible with both Python 2 and Python 3. Make sure you install `subprocess32` if you want to use the former.
## Instructions ##
CPU and cache parameters have to be set in the `simparams.py` file. Many other options can be passed as command-line arguments.
Execute with option `-h` to show the help.