https://github.com/arturmareknowak/systemverilog

Simulations created during participation in ALICE project
https://github.com/arturmareknowak/systemverilog

alice-experiment fpga

Last synced: 4 days ago
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Simulations created during participation in ALICE project

• Host: GitHub
• URL: https://github.com/arturmareknowak/systemverilog
• Owner: ArturMarekNowak
• Created: 2020-07-09T18:47:53.000Z (over 4 years ago)
• Default Branch: master
• Last Pushed: 2020-08-05T12:25:13.000Z (over 4 years ago)
• Last Synced: 2023-03-05T22:56:02.270Z (almost 2 years ago)
• Topics: alice-experiment, fpga
• Language: SystemVerilog
• Homepage:
• Size: 26.4 KB
• Stars: 0
• Watchers: 2
• Forks: 0
• Open Issues: 0

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