https://github.com/arturmareknowak/taylorseriesfpga
This project is an implementation of Taylor Series in System Verilog
https://github.com/arturmareknowak/taylorseriesfpga
fpga taylor-series zynq
Last synced: about 1 month ago
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This project is an implementation of Taylor Series in System Verilog
- Host: GitHub
- URL: https://github.com/arturmareknowak/taylorseriesfpga
- Owner: ArturMarekNowak
- License: mit
- Created: 2021-05-18T15:58:59.000Z (about 4 years ago)
- Default Branch: master
- Last Pushed: 2021-10-10T13:11:28.000Z (over 3 years ago)
- Last Synced: 2023-03-05T22:56:02.244Z (about 2 years ago)
- Topics: fpga, taylor-series, zynq
- Language: SystemVerilog
- Homepage:
- Size: 16.6 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0