https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga
artix artix-7 axi axi-lite axi-memory-mapped axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado
Last synced: 7 months ago
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A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
- Host: GitHub
- URL: https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga
- Owner: aryan-programmer
- Created: 2023-11-21T10:36:10.000Z (almost 2 years ago)
- Default Branch: main
- Last Pushed: 2023-11-21T11:14:18.000Z (almost 2 years ago)
- Last Synced: 2025-01-17T04:12:37.838Z (9 months ago)
- Topics: artix, artix-7, axi, axi-lite, axi-memory-mapped, axi-stream, basys3, embedded, fpga, hls, vitis, vitis-hls, vivado, vivado-ip-integrator, vivado-vitis, xilinx, xilinx-fpga, xilinx-hls, xilinx-vitis, xilinx-vivado
- Language: TeX
- Homepage:
- Size: 191 KB
- Stars: 2
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files: