https://github.com/asadiahmad/alu-8bit

ALU Verilog Project calculate add, subtract, increment, decrement, multiply
https://github.com/asadiahmad/alu-8bit

alu hardware verilog

Last synced: about 2 months ago
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ALU Verilog Project calculate add, subtract, increment, decrement, multiply

• Host: GitHub
• URL: https://github.com/asadiahmad/alu-8bit
• Owner: AsadiAhmad
• License: mit
• Created: 2024-04-10T19:37:43.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2025-03-16T11:11:47.000Z (7 months ago)
• Last Synced: 2025-07-04T06:07:37.077Z (3 months ago)
• Topics: alu, hardware, verilog
• Language: Verilog
• Homepage:
• Size: 422 KB
• Stars: 27
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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# ALU-8Bit

ALU Verilog Project calculate add, subtract, increment, decrement, multiply