https://github.com/ashleynewson/SmartSim

Design and simulate digital logic circuits of varying complexity.
https://github.com/ashleynewson/SmartSim

Last synced: 24 days ago
JSON representation

Design and simulate digital logic circuits of varying complexity.

• Host: GitHub
• URL: https://github.com/ashleynewson/SmartSim
• Owner: ashleynewson
• License: gpl-3.0
• Created: 2012-07-27T15:42:20.000Z (over 12 years ago)
• Default Branch: master
• Last Pushed: 2023-10-14T14:01:53.000Z (about 1 year ago)
• Last Synced: 2024-08-05T10:13:10.288Z (4 months ago)
• Language: C
• Homepage: smartsim.org.uk
• Size: 2.63 MB
• Stars: 186
• Watchers: 25
• Forks: 30
• Open Issues: 4
• Metadata Files:
  • Readme: README.md
  • Changelog: ChangeLog
  • License: COPYING

Awesome Lists containing this project

README

        
SmartSim

========

SmartSim is a digital logic circuit design and simulation package.

Features

--------

* Designing circuits using your own custom components.

* Simulating circuits interactively, with the ability to explore

  inside custom components.

* Creating logic timing diagrams from simulations.

* Create circuits with loadable and saveable RAM/ROM.

* Exporting your design or timing diagram to PNG, PDF, and SVG.

* Plug-in components for expanding circuit capabilities.

Website: http://www.smartsim.org.uk/

Maintainer: [email protected]