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https://github.com/assem-elqersh/mips-processor-designs
Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.
https://github.com/assem-elqersh/mips-processor-designs
computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog
Last synced: about 19 hours ago
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Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.
- Host: GitHub
- URL: https://github.com/assem-elqersh/mips-processor-designs
- Owner: Assem-ElQersh
- License: mit
- Created: 2025-01-25T08:47:52.000Z (2 days ago)
- Default Branch: main
- Last Pushed: 2025-01-25T08:49:59.000Z (2 days ago)
- Last Synced: 2025-01-25T09:25:22.468Z (2 days ago)
- Topics: computer-architecture, educational, hardware-designs, mips, mips-architecture, processor-design, simulation, verilog
- Language: Verilog
- Homepage:
- Size: 0 Bytes
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# MIPS-Processor-Designs
Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.