https://github.com/ataradov/riscv

Verilog implementation of a RISC-V core
https://github.com/ataradov/riscv

Last synced: about 2 months ago
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Verilog implementation of a RISC-V core

• Host: GitHub
• URL: https://github.com/ataradov/riscv
• Owner: ataradov
• License: bsd-3-clause
• Created: 2018-01-07T18:20:46.000Z (over 6 years ago)
• Default Branch: master
• Last Pushed: 2018-10-11T02:10:43.000Z (almost 6 years ago)
• Last Synced: 2024-06-11T00:13:20.928Z (3 months ago)
• Language: Verilog
• Size: 52.7 KB
• Stars: 98
• Watchers: 14
• Forks: 19
• Open Issues: 0

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