https://github.com/atoomnetmarc/risc-v-emulator-native

RISC-V-emulator implementation useable for RISCOF riscv-arch-test.
https://github.com/atoomnetmarc/risc-v-emulator-native

emulator linux platformio risc-v

Last synced: about 12 hours ago
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RISC-V-emulator implementation useable for RISCOF riscv-arch-test.

• Host: GitHub
• URL: https://github.com/atoomnetmarc/risc-v-emulator-native
• Owner: atoomnetmarc
• License: apache-2.0
• Created: 2024-03-26T18:15:27.000Z (10 months ago)
• Default Branch: main
• Last Pushed: 2024-09-16T18:07:05.000Z (5 months ago)
• Last Synced: 2024-09-16T22:18:34.857Z (5 months ago)
• Topics: emulator, linux, platformio, risc-v
• Language: C
• Homepage:
• Size: 87.9 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# Description

This is an implementation of my [RISC-V cpu emulator](https://github.com/atoomnetmarc/RISC-V-emulator) that can compile into an operating system executable using [PlatformIO Native development platform](https://docs.platformio.org/en/latest/platforms/native.html).

It is used for generating signature files that the [RISCOF](https://riscof.readthedocs.io/) test suite can test against the tests defined in [riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test).

The resulting report.html that RISCOF generates gives an overview of RISV-V instructions that behave correctly or ones that need some work.

# Notes to self

Symlink the build executable called `program` to `/usr/local/bin/rve`.

Execute `rve` in the same directory as where `dut-rom.bin` (the RISC-V ROM image) and `dut-ram.bin` (the RISC-V RAM default values) exist. After executing you should get `dut-ram-after.bin`.

[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)