https://github.com/aturley/risc16
Verilog implementation of a 16-bit RISC as described in https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf
https://github.com/aturley/risc16
Last synced: 7 months ago
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Verilog implementation of a 16-bit RISC as described in https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf
- Host: GitHub
- URL: https://github.com/aturley/risc16
- Owner: aturley
- Created: 2022-06-08T19:44:57.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-06-21T03:47:11.000Z (over 3 years ago)
- Last Synced: 2025-01-28T10:51:32.270Z (8 months ago)
- Language: Assembly
- Size: 24.4 KB
- Stars: 3
- Watchers: 3
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
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README
# RISC16
## Overview
This is a Verilog implemenation of [a 16-bit RISC](https://user.eng.umd.edu/~blj/RiSC/RiSC-isa.pdf).
## Status
The LW and ADD instructions have been implemented.
## Building and Running
Build the CPU and testbench:
```sh
iverilog -o cpu.vvp cpu.v cpu_tb.v
```
Run it in the simulator:
```sh
vvp cpu.vvp
```
## Building and running the assembler
```sh
clang -std=c11 -Wall -Werror -o assembler assembler.c
```
Run assembler to generate ascii text file with hex bytecode.
The output file should be compatible with $readmemh so that we can load it into instruction memory.
``` sh
assembler test_assembly.s test.hex
```