https://github.com/awrsha/logical-circuit-laboratory
verilog exercises for LC Lab at Qazvin islamic azad university
https://github.com/awrsha/logical-circuit-laboratory
modelsim verilog
Last synced: 7 months ago
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verilog exercises for LC Lab at Qazvin islamic azad university
- Host: GitHub
- URL: https://github.com/awrsha/logical-circuit-laboratory
- Owner: Awrsha
- Created: 2023-01-06T16:19:59.000Z (almost 3 years ago)
- Default Branch: master
- Last Pushed: 2023-08-15T20:27:52.000Z (about 2 years ago)
- Last Synced: 2024-02-27T18:33:04.623Z (over 1 year ago)
- Topics: modelsim, verilog
- Language: Verilog
- Homepage:
- Size: 17.6 KB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md