https://github.com/ayeshathoi/dld-206

Digital Logic Design
https://github.com/ayeshathoi/dld-206

adder-subtractor asynchronous comparator counter encoder flip-flops k-map multiplexer simulation synchronous-circuits truth-table

Last synced: 6 months ago
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Digital Logic Design

• Host: GitHub
• URL: https://github.com/ayeshathoi/dld-206
• Owner: ayeshathoi
• Created: 2024-06-23T20:27:43.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2024-06-24T16:45:13.000Z (over 1 year ago)
• Last Synced: 2025-01-02T00:23:52.172Z (about 1 year ago)
• Topics: adder-subtractor, asynchronous, comparator, counter, encoder, flip-flops, k-map, multiplexer, simulation, synchronous-circuits, truth-table
• Homepage:
• Size: 4.69 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

Awesome Lists containing this project

README

          
## **`CSE 206` : Digital Logic Design Sessional**

- [Truth Table using Boolean Algebra Offline 1](https://github.com/ayeshathoi/DLD-206/tree/main/1_Offline)

- [Comparator, adder / subtractor Offline 2](https://github.com/ayeshathoi/DLD-206/tree/main/2_Offline)

- [Flip-Flops and Registers Offline 3](https://github.com/ayeshathoi/DLD-206/tree/main/3_Offline)

- [K-map Online](https://github.com/ayeshathoi/DLD-206/tree/main/2_Online)

- [Multiplexer Online](https://github.com/ayeshathoi/DLD-206/tree/main/3_Online)

- [Encoder Online](https://github.com/ayeshathoi/DLD-206/tree/main/4_Online)

- [Basic Counter Online](https://github.com/ayeshathoi/DLD-206/tree/main/5_Online)

- [Sequence Counter Online](https://github.com/ayeshathoi/DLD-206/tree/main/6_Online)

- [Synchronous Sequential Circuit Online](https://github.com/ayeshathoi/DLD-206/tree/main/7_Online)

- [Asynchronous Sequential Circuit Online](https://github.com/ayeshathoi/DLD-206/tree/main/8_Online)

- *Offline Assignments Collaborator* : 


    - Noshin Nawal (1805061)

    - K M Asifur Rahman (1805063)

    - Sanju Basak (1805064)

    - Sayeed Hasan Ovi (1805065)