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https://github.com/ayushpatel2026/fpga-programming
https://github.com/ayushpatel2026/fpga-programming
Last synced: 22 days ago
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- Host: GitHub
- URL: https://github.com/ayushpatel2026/fpga-programming
- Owner: Ayushpatel2026
- Created: 2024-11-27T01:29:23.000Z (27 days ago)
- Default Branch: main
- Last Pushed: 2024-11-27T01:46:16.000Z (27 days ago)
- Last Synced: 2024-11-27T02:32:15.410Z (27 days ago)
- Language: Verilog
- Size: 4.88 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# FPGA Programming
This repository contains Verilog code developed for programming FPGA boards using **Intel Quartus**. These projects were created as part of my hardware design course and showcase modular design principles and practical digital logic implementations. Key projects include a **Combination Lock** and an **Arithmetic Logic Unit (ALU)**.
## Overview
The projects in this repository demonstrate:
- **FPGA Programming Skills**: Hands-on experience with Verilog HDL and FPGA deployment.
- **Modular Code Design**: Each project emphasizes reusable and clean Verilog modules.
- **Practical Applications**: Designs simulate and implement real-world functionality on FPGA boards.## Projects
### **1. Combination Lock**
A fully functional **combination lock** with robust features:
- **Stores a Combination**: Allows users to set and save a unique combination.
- **Incorrect Attempts Handling**: Triggers an alarm after two incorrect tries.
- **Reset Functionality**: Enables users to set a new combination when needed.
- **Key Highlights**:
- Demonstrates modular Verilog design with well-structured code.
- Incorporates finite state machines (FSMs) for control logic.### **2. Arithmetic Logic Unit (ALU)**
A simple **3-bit ALU** designed for FPGA implementation:
- **Addition Operation**: Adds two 3-bit binary numbers.
- **Output Display**: Results are shown on a **7-segment display**.
- **Registers**: Uses registers to store input and output values.
- **Key Highlights**:
- Demonstrates basic arithmetic operations and display logic.