https://github.com/balos1/fpga-sparse-matrix-mult

A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.
https://github.com/balos1/fpga-sparse-matrix-mult

fpga matrix-factorization sparse-matrices sparse-matrix

Last synced: 24 days ago
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A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.

• Host: GitHub
• URL: https://github.com/balos1/fpga-sparse-matrix-mult
• Owner: balos1
• Created: 2017-11-11T05:30:08.000Z (about 7 years ago)
• Default Branch: master
• Last Pushed: 2017-12-14T07:36:47.000Z (about 7 years ago)
• Last Synced: 2024-10-29T16:59:39.265Z (2 months ago)
• Topics: fpga, matrix-factorization, sparse-matrices, sparse-matrix
• Language: SystemVerilog
• Homepage:
• Size: 3.07 MB
• Stars: 5
• Watchers: 3
• Forks: 2
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
Sparse Matrix Multiplication Coprocessor

===

A sparse matrix multiplication FPGA architecture which acts as a 'coprocessor'.

# Authors

University of the Pacific, Department of Electrical and Computer Engineering

[Cody Balos](https://github.com/cojomojo), [Crystal Beltran-Sanchez](https://github.com/CrystalBS), [Kelvin Hu](https://github.com/monootc)

# References

[1] [Jamro, E., Pabiś, T., Russek, P., Wiatr, K.: The Algorithms for FPGA Implementation of Sparse Matrices Multiplication. Comput. Inform.](https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&uact=8&ved=0ahUKEwjUy5GSg9fXAhXJiFQKHcWHB3oQFgg7MAM&url=http%3A%2F%2Fwww.cai.sk%2Fojs%2Findex.php%2Fcai%2Farticle%2Fdownload%2F2795%2F645&usg=AOvVaw261Vm0t0HTx79NnRHqKLta)

# About

Created as Fall 2017 ECPE 194 (Advanced Digital Design) finalproject.