https://github.com/baochuquan/riscv-mmu
https://github.com/baochuquan/riscv-mmu
Last synced: 4 months ago
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- Host: GitHub
- URL: https://github.com/baochuquan/riscv-mmu
- Owner: baochuquan
- Created: 2017-03-13T12:05:29.000Z (over 8 years ago)
- Default Branch: master
- Last Pushed: 2017-11-05T11:56:55.000Z (over 7 years ago)
- Last Synced: 2025-01-09T09:28:00.197Z (5 months ago)
- Language: Verilog
- Size: 6.29 MB
- Stars: 14
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
使用Verilog重写RISC-V Rocket
Chip的MMU结构。该结构内部包含一个I-TLB、一个D-TLB和一个PTW模块。以此对比Chisel自动生成的Verilog设计与手写的Verilog设计的差异。