https://github.com/barannmeisterr/32-bit-alu-design
This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic
https://github.com/barannmeisterr/32-bit-alu-design
alu arithmetic-logic-unit computerorganization fulladder inverter logic-gates multiplexer mux systemverilog verilog
Last synced: 17 days ago
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This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic
- Host: GitHub
- URL: https://github.com/barannmeisterr/32-bit-alu-design
- Owner: barannmeisterr
- License: mit
- Created: 2024-11-02T11:32:48.000Z (12 months ago)
- Default Branch: main
- Last Pushed: 2024-11-02T11:40:09.000Z (12 months ago)
- Last Synced: 2025-05-16T22:14:28.222Z (5 months ago)
- Topics: alu, arithmetic-logic-unit, computerorganization, fulladder, inverter, logic-gates, multiplexer, mux, systemverilog, verilog
- Language: SystemVerilog
- Homepage:
- Size: 57.6 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0