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https://github.com/bartpleiter/fpgc6

Redesign and continuation of the FPGC5 but with a pipelined CPU (with hazard detection, branch prediction, etc.), memory cache (L1 and L2), and a better architecture for running BCC code
https://github.com/bartpleiter/fpgc6

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Redesign and continuation of the FPGC5 but with a pipelined CPU (with hazard detection, branch prediction, etc.), memory cache (L1 and L2), and a better architecture for running BCC code

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# FPGC6

[![FPGC Logo](Documentation/docs/images/logo_big_alpha.png)](https://www.b4rt.nl/fpgc/)

[Project Wiki](https://www.b4rt.nl/fpgc/)