https://github.com/benlent123/5eic0-comparc

TU/E related course repo (5EIC0)
https://github.com/benlent123/5eic0-comparc

assembly c fpga fsm risc-v tue verilog vhdl

Last synced: about 2 months ago
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TU/E related course repo (5EIC0)

• Host: GitHub
• URL: https://github.com/benlent123/5eic0-comparc
• Owner: BenLent123
• Created: 2025-02-11T16:08:11.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2025-04-11T13:23:02.000Z (about 1 year ago)
• Last Synced: 2025-04-12T04:59:31.529Z (about 1 year ago)
• Topics: assembly, c, fpga, fsm, risc-v, tue, verilog, vhdl
• Language: Verilog
• Homepage:
• Size: 854 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README

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README

          
This repo covers most of the 2024/2025 version of the 5EIC0 computer architecture course. It does not cover all things related to FPGAs. For more help, go to OffCourse!

- entire practice exam  (done + tested)

- entire offcourse FSM page (done + tested)

- entire offcourse FSM quiz (done + tested)

- entire offcourse riscV assembly (done + tested)

- riscV assembly assignments (done+tested)

- all labs except riscV lab 3 (done+tested)

- thor exam practice (done + tested)

- links to offcourse and another git repo are given!

This repo will probably not be continuously updated! 

- last updated x.04.2025 !

                      good luck 0_0

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