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https://github.com/benmezger/strail
A kernel with support to the RISCV architecture
https://github.com/benmezger/strail
asm c kernel operating-system riscv unix
Last synced: about 2 months ago
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A kernel with support to the RISCV architecture
- Host: GitHub
- URL: https://github.com/benmezger/strail
- Owner: benmezger
- Created: 2020-01-13T16:10:44.000Z (almost 5 years ago)
- Default Branch: develop
- Last Pushed: 2020-11-14T06:22:38.000Z (about 4 years ago)
- Last Synced: 2023-10-20T18:12:08.051Z (about 1 year ago)
- Topics: asm, c, kernel, operating-system, riscv, unix
- Language: C
- Homepage:
- Size: 47.9 KB
- Stars: 7
- Watchers: 2
- Forks: 1
- Open Issues: 2
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Metadata Files:
- Readme: README.md
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README
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# strail
A Kernel with suport to the RISC-V ISA# Introduction
I wrote a small kernel for my bachelor thesis with support to the RISC-V ISA, focussing
at the education of operating systems, where students and professors may dive into a
simpler kernel implementation for academic puposes, instead of relying on large kernel code-base.
We hope this project might give students and professors a big picture of the implementation of
an operating systems and how components communicate with each other.Although I only had 1 year to write and develop my thesis, it was enough time for
me to write a small and basic kernel with RISC-V's {machine, supervisor, user}-mode
support, trap handlers and a basic round-robin scheduling algorithm.
I was approved upon the presentation of my thesis, but I decided to refactor
the code and allow multiple architecture support, better code organization, a kernel
interface for communicating with the lower level architectural code and better trap
handlers and smoother POSIX support.# Supported ISA's
- [X] RISCV
# Instruction Set Architecture (ISA)
## RISC-V
- Enter `main` through `_start`
- `DIRECT MODE` access to trap handlers
- Enter machine-mode