https://github.com/bespoke-silicon-group/bsg_ddr3_io

BaseJump DDR3 I/O Design
https://github.com/bespoke-silicon-group/bsg_ddr3_io

Last synced: 2 months ago
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BaseJump DDR3 I/O Design

• Host: GitHub
• URL: https://github.com/bespoke-silicon-group/bsg_ddr3_io
• Owner: bespoke-silicon-group
• License: bsd-3-clause
• Created: 2021-12-15T20:41:02.000Z (about 3 years ago)
• Default Branch: main
• Last Pushed: 2023-03-06T17:04:27.000Z (almost 2 years ago)
• Last Synced: 2024-08-03T17:11:29.780Z (6 months ago)
• Language: Python
• Size: 705 KB
• Stars: 4
• Watchers: 16
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

Awesome Lists containing this project

• awesome-opensource-hardware - bsg_ddr3_io

README

        
# DDR3 SSTL Design for SKY130

This repo contains a DDR3 SSTL driver circuit designed for the Skywater 130nm PDK.

Introduction and design overview found [here](docs/).

Installation simulation script instructions [here](docs/simulation_scripts.md).   

PDK installation instructions found [here](docs/pdk_installation.md).

Directory structure:

* `schem`   Xschem schematic files for SSTL design.

* `layout`  Magic format layout files for SSTL design.

* `scripts` Simulation handling and automation Python scripts.

* `docs`    Some extra documentation files.

* `sky130`  Sky130 specific files (standard cell "include" files.)

* `spice`   Output directory for spice scripts generated by Xschem.

* `out`     Output directory for simulation results.

* `tools`   Instillation directory for the open source DEA tools used for design and simulation.

## Implementation

This circuit was implemented in a Efabless MPW-5 project which can be found in ([this repo](https://github.com/derekcom17/caravel_user_project_ddr3_sstl)).