https://github.com/betarixm/csed311

POSTECH: Computer Architecture (Spring 2021)
https://github.com/betarixm/csed311

architecture cpu postech

Last synced: 3 months ago
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POSTECH: Computer Architecture (Spring 2021)

• Host: GitHub
• URL: https://github.com/betarixm/csed311
• Owner: betarixm
• Created: 2021-03-05T15:18:55.000Z (about 4 years ago)
• Default Branch: master
• Last Pushed: 2021-06-01T02:47:53.000Z (almost 4 years ago)
• Last Synced: 2025-01-19T09:44:26.665Z (4 months ago)
• Topics: architecture, cpu, postech
• Language: Verilog
• Homepage:
• Size: 10.6 MB
• Stars: 2
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Computer Architecture

[![CSED311@POSTECH](https://img.shields.io/badge/CSED311-POSTECH-c80150)](https://www.postech.ac.kr/eng)

[![CSED311@POSTECH](https://img.shields.io/badge/Spring-2021-775E64)](https://www.postech.ac.kr/eng)

**Computer Architecture** is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance, and cost goals. This course introduces the basic principles and hardware structures of a modern general-purpose computer. We will learn, for example, how to design the control and datapath for a pipelined RISC processor and how to design fast memory and storage systems. The principles presented in the lectures are reinforced in the laboratory through designing and implementing a RISC processor in Register Transfer-Level (RTL) using Verilog HDL.

## Assignments

### ALU

[Link](Lab/Lab01)

### RTL Design

Simple vending machine FSM implementation with Verilog.

[Link](Lab/Lab01)

### Single Cycle CPU

![datapath](Lab/Lab03/report/datapath.png)

[Link](Lab/Lab03)

### Multi Cycle CPU

![datapath](Lab/Lab04/report/datapath.png)

[Link](Lab/Lab04)

### Pipeline CPU

![datapath](Lab/Lab05/report/datapath.png)

[Link](Lab/Lab05)

### Cache

[Link](Lab/Lab06)

### DMA

[Link](Lab/Lab07)