https://github.com/bhargav191098/stopwatch-hdl-verilog

The project uses HDL to simulate a stop watch! :D
https://github.com/bhargav191098/stopwatch-hdl-verilog

Last synced: 21 days ago
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The project uses HDL to simulate a stop watch! :D

• Host: GitHub
• URL: https://github.com/bhargav191098/stopwatch-hdl-verilog
• Owner: bhargav191098
• Created: 2017-11-17T14:01:37.000Z (almost 7 years ago)
• Default Branch: master
• Last Pushed: 2017-11-17T14:38:58.000Z (almost 7 years ago)
• Last Synced: 2023-07-07T07:34:58.733Z (over 1 year ago)
• Language: Verilog
• Size: 1000 Bytes
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0

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