https://github.com/biged/cpu-65org16
6502-like CPU core with 16-bit data and 32-bit address in Verilog
https://github.com/biged/cpu-65org16
Last synced: 4 months ago
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6502-like CPU core with 16-bit data and 32-bit address in Verilog
- Host: GitHub
- URL: https://github.com/biged/cpu-65org16
- Owner: BigEd
- Created: 2011-05-29T09:18:11.000Z (about 15 years ago)
- Default Branch: master
- Last Pushed: 2015-11-03T10:21:28.000Z (over 10 years ago)
- Last Synced: 2025-07-18T23:37:54.692Z (11 months ago)
- Homepage: https://github.com/BigEd/verilog-6502
- Size: 121 KB
- Stars: 5
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README
Awesome Lists containing this project
README
This project is a placeholder because the 65Org16 is a fork of
verilog-6502 by Arlet Ottens
Please go there and have a look!
https://github.com/BigEd/verilog-6502
The 65Org16 is a CPU core with:
- 32-bit address space
- by using 16-bit bytes
- with no specific support for 8-bit bytes
- with BCD mode as unspecified behaviour
- and otherwise all opcodes and addressing modes like NMOS 6502
This core has run at 50MHz on FPGA but is still early stage.
For some example software, see http://biged.github.io/6502-website-archives/lowkey.comuf.com/
The license is LGPL