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https://github.com/bipinoli/vericlash

Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them
https://github.com/bipinoli/vericlash

clash-lang haskell verilog

Last synced: 11 days ago
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Implementation of bunch of circuits in Haskell (Clash) and Verilog to learn and compare them

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# Bunch of circuits in Verilog and in Clash to learn and compare them

### Combinational
- [8-bit ripple carry adder](https://github.com/Bipinoli/VeriClash/tree/main/combinational/EightBitAdder)
- [8-to-3 Bit Priority Encoder](https://github.com/Bipinoli/VeriClash/tree/main/combinational/PriorityEncoder)

### Sequential
- [4-bit counter](https://github.com/Bipinoli/VeriClash/tree/main/sequential/FourBitCounter)
- [Bidirectional Shift Register](https://github.com/Bipinoli/VeriClash/tree/main/sequential/BidirectionalShiftRegister)
- [Traffic light controller - Moore machine](https://github.com/Bipinoli/VeriClash/tree/main/sequential/TrafficLight)

### Memory
- [Ring buffer (FIFO)](https://github.com/Bipinoli/VeriClash/tree/main/memory/RingBuffer)

### Digital Signal Processing
- [FIR filter](https://github.com/Bipinoli/VeriClash/tree/main/signal_processing/FirFilter)

### CPU
- [CPU in Clash based on my older verilog design (VeriRISCy)](https://github.com/Bipinoli/VeriClash/tree/main/cpu)

### Others
- [Matrix multiplier](https://github.com/Bipinoli/VeriClash/tree/main/other/MatrixMultiplier)

## Steps to run:

I am running Clash in minimal setup with `clashi`.

1. Setup clash by running `setup_clash.sh`. This need to be run only once.
2. Run `run.sh` in a desired project and follow the instructions there