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https://github.com/birdybro/cegen_sv
Simple synchronous 50% duty cycle clock generator with external division factor parameter, written in SystemVerilog
https://github.com/birdybro/cegen_sv
Last synced: 17 days ago
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Simple synchronous 50% duty cycle clock generator with external division factor parameter, written in SystemVerilog
- Host: GitHub
- URL: https://github.com/birdybro/cegen_sv
- Owner: birdybro
- License: mit
- Created: 2023-09-19T04:30:13.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2023-09-19T04:30:49.000Z (over 1 year ago)
- Last Synced: 2024-12-01T07:07:21.136Z (22 days ago)
- Language: SystemVerilog
- Size: 2.93 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0