https://github.com/birdybro/fir_filter_sv

Work in progress FIR Filter written in SystemVerilog
https://github.com/birdybro/fir_filter_sv

Last synced: 17 days ago
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Work in progress FIR Filter written in SystemVerilog

• Host: GitHub
• URL: https://github.com/birdybro/fir_filter_sv
• Owner: birdybro
• License: mit
• Created: 2023-09-17T14:54:22.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2023-09-25T21:38:46.000Z (about 1 year ago)
• Last Synced: 2024-12-01T07:07:24.863Z (22 days ago)
• Language: Python
• Homepage:
• Size: 34.9 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

        
# FIR_Filter_sv

Not working currently, work in progress... soon... eventually...

FIR Filter written in SystemVerilog

by Kevin Coleman (birdybro)

I may make it more parameterizable later, it's not a major priority currently, just got it to the point where I can synthesize it and use it in the [MiSTer FPGA MegaDrive core](https://github.com/MiSTer-devel/MegaDrive_MiSTer).

Written by an amateur who just learned about audio filtering over the course of a week.

Written with the assistance of ChatGPT and Google Bard as I try to see how much AI can be used for daily. AI querying is a good skill to ihave.