https://github.com/blagojeblagojevic/vga_verilog

Implementation of a vga interface on a Basys 3 FPGA
https://github.com/blagojeblagojevic/vga_verilog

fpga verilog

Last synced: 18 days ago
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Implementation of a vga interface on a Basys 3 FPGA

• Host: GitHub
• URL: https://github.com/blagojeblagojevic/vga_verilog
• Owner: BlagojeBlagojevic
• Created: 2023-04-24T13:03:53.000Z (over 1 year ago)
• Default Branch: main
• Last Pushed: 2023-04-24T13:13:08.000Z (over 1 year ago)
• Last Synced: 2023-04-24T16:29:13.808Z (over 1 year ago)
• Topics: fpga, verilog
• Language: Verilog
• Homepage:
• Size: 113 KB
• Stars: 1
• Watchers: 1
• Forks: 0
• Open Issues: 0

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