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https://github.com/bluespec/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
https://github.com/bluespec/Piccolo
Last synced: 3 months ago
JSON representation
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
- Host: GitHub
- URL: https://github.com/bluespec/Piccolo
- Owner: bluespec
- License: apache-2.0
- Created: 2018-05-29T20:35:53.000Z (over 6 years ago)
- Default Branch: master
- Last Pushed: 2022-01-23T23:41:45.000Z (almost 3 years ago)
- Last Synced: 2024-08-01T01:27:46.566Z (6 months ago)
- Language: Verilog
- Size: 11.9 MB
- Stars: 302
- Watchers: 24
- Forks: 49
- Open Issues: 16
Awesome Lists containing this project
- awesome-riscv - Piccolo@bluespec - stage in-order|ASIC|Apache| (Open Source Core Implementations)