https://github.com/bucknalla/ad9361_zycap

PL Layer Controls for the AD9361 RF Front End
https://github.com/bucknalla/ad9361_zycap

ad9361 fmcomms3 xilinx-fpga zedboard

Last synced: 8 months ago
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PL Layer Controls for the AD9361 RF Front End

• Host: GitHub
• URL: https://github.com/bucknalla/ad9361_zycap
• Owner: Bucknalla
• License: mit
• Created: 2018-02-08T10:36:24.000Z (over 7 years ago)
• Default Branch: master
• Last Pushed: 2018-02-08T17:16:02.000Z (over 7 years ago)
• Last Synced: 2025-01-09T05:45:45.112Z (9 months ago)
• Topics: ad9361, fmcomms3, xilinx-fpga, zedboard
• Size: 747 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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README

          
# AD9361_ZyCAP

PL Layer Controls for the AD9361 RF Front End