https://github.com/bucknalla/axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files
https://github.com/bucknalla/axis-interfacer

axi axi-lite axis verilog xilinx

Last synced: 8 months ago
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Extract AXI (Full, Lite and Stream) interfaces from Verilog source files

• Host: GitHub
• URL: https://github.com/bucknalla/axis-interfacer
• Owner: Bucknalla
• Created: 2020-04-28T10:10:00.000Z (over 5 years ago)
• Default Branch: master
• Last Pushed: 2020-06-11T10:55:54.000Z (over 5 years ago)
• Last Synced: 2025-01-09T05:45:45.034Z (9 months ago)
• Topics: axi, axi-lite, axis, verilog, xilinx
• Size: 37.1 KB
• Stars: 1
• Watchers: 2
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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# axis-interfacer

Extract AXI (Full, Lite and Stream) interfaces from Verilog source files