https://github.com/bugenzhao/mips
👨🏻💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.
https://github.com/bugenzhao/mips
mips simulator verilog
Last synced: 6 months ago
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👨🏻💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.
- Host: GitHub
- URL: https://github.com/bugenzhao/mips
- Owner: BugenZhao
- Created: 2020-05-23T14:48:33.000Z (about 6 years ago)
- Default Branch: master
- Last Pushed: 2020-07-02T04:12:29.000Z (almost 6 years ago)
- Last Synced: 2025-03-15T04:49:32.949Z (over 1 year ago)
- Topics: mips, simulator, verilog
- Language: Verilog
- Homepage:
- Size: 2.59 MB
- Stars: 2
- Watchers: 1
- Forks: 0
- Open Issues: 0