https://github.com/cachouuu/uartofpic16f1826
https://github.com/cachouuu/uartofpic16f1826
assembly systemverilog
Last synced: 19 days ago
JSON representation
- Host: GitHub
- URL: https://github.com/cachouuu/uartofpic16f1826
- Owner: cachouuu
- Created: 2025-02-25T08:47:59.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-02-25T09:37:17.000Z (over 1 year ago)
- Last Synced: 2025-02-25T09:39:01.445Z (over 1 year ago)
- Topics: assembly, systemverilog
- Language: SystemVerilog
- Homepage:
- Size: 0 Bytes
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
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Metadata Files: