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https://github.com/calint/tang-nano-9k--step-10

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Host: GitHub
URL: https://github.com/calint/tang-nano-9k--step-10
Owner: calint
Created: 2024-06-12T15:47:42.000Z (5 months ago)
Default Branch: main
Last Pushed: 2024-06-15T10:26:06.000Z (5 months ago)
Last Synced: 2024-06-15T22:03:45.930Z (5 months ago)
Language: Verilog
Size: 1.92 MB
Stars: 0
Watchers: 1
Forks: 0
Open Issues: 0
Metadata Files:
- Readme: README.md

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README

        # Tang Nano 9K

step-wise development towards a RISC-V rv32i implementation supporting cache of PSRAM

## todo

```

[x] step 9: read from flash, write to cache

[ ] step 10: implement ram interface

[x]   writing to UART address triggers cache fetch line

      => cache.enable added

[ ] step 11: adapt riscv core

```