https://github.com/calint/tang-nano-9k--step-8

https://github.com/calint/tang-nano-9k--step-8

Last synced: 3 days ago
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• Host: GitHub
• URL: https://github.com/calint/tang-nano-9k--step-8
• Owner: calint
• Created: 2024-06-07T18:58:51.000Z (5 months ago)
• Default Branch: main
• Last Pushed: 2024-06-10T17:18:03.000Z (5 months ago)
• Last Synced: 2024-06-10T21:06:33.514Z (5 months ago)
• Language: Verilog
• Size: 1.39 MB
• Stars: 0
• Watchers: 1
• Forks: 0
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
# Tang Nano 9K

step-wise development towards a RISC-V rv32i implementation supporting cache of PSRAM

## todo

```

[ ] test: cache read and write in 1 cycle; led if ok else hang

[ ] test: cache: write, write with evict, read with evict, read with evict the byte written

[ ] cache: read and 'data_out_ready' can be done while command interval delay active

[ ] cache: wait_before_read, wait_after_read, wait_before_write, wait_after_write signals

    instead of generic 'busy' and optimizing access to cached data when writing

[ ] step 9: read from flash and assert with led

[ ] step 10: read from flash, write to cache

[ ] step 11: implement ram interface

[ ] step 12: adapt riscv core

```