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https://github.com/calint/tang-nano-9k--step-9
https://github.com/calint/tang-nano-9k--step-9
Last synced: 3 days ago
JSON representation
- Host: GitHub
- URL: https://github.com/calint/tang-nano-9k--step-9
- Owner: calint
- Created: 2024-06-12T05:19:52.000Z (5 months ago)
- Default Branch: main
- Last Pushed: 2024-06-12T15:41:50.000Z (5 months ago)
- Last Synced: 2024-06-13T14:46:51.831Z (5 months ago)
- Language: Verilog
- Size: 962 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
Awesome Lists containing this project
README
# Tang Nano 9K
step-wise development towards a RISC-V rv32i implementation supporting cache of PSRAM
## todo
```
[x] step 9: read from flash, write to cache
[ ] step 10: implement ram interface
[ ] step 11: adapt riscv core
```