https://github.com/carlkidcrypto/digital-systems-engineering
A repo for ECE 440 (Digital Systems Engineering) class projects
https://github.com/carlkidcrypto/digital-systems-engineering
systemverilog verilog xilinx-vivado zynq
Last synced: 6 months ago
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A repo for ECE 440 (Digital Systems Engineering) class projects
- Host: GitHub
- URL: https://github.com/carlkidcrypto/digital-systems-engineering
- Owner: carlkidcrypto
- License: mit
- Created: 2020-01-18T00:37:43.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2020-04-17T18:46:29.000Z (over 5 years ago)
- Last Synced: 2023-03-22T06:15:44.579Z (over 2 years ago)
- Topics: systemverilog, verilog, xilinx-vivado, zynq
- Language: VHDL
- Size: 44.3 MB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0