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https://github.com/carloscraveiro/alu_fgpa_cyciv
ALU (Arithmetic Logic Unit) made with Verilog using Intel-Quartus for one Cyclone IV FPGA dev-kit (made with a learning proupose / personal project)
https://github.com/carloscraveiro/alu_fgpa_cyciv
Last synced: 2 days ago
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ALU (Arithmetic Logic Unit) made with Verilog using Intel-Quartus for one Cyclone IV FPGA dev-kit (made with a learning proupose / personal project)
- Host: GitHub
- URL: https://github.com/carloscraveiro/alu_fgpa_cyciv
- Owner: CarlosCraveiro
- License: gpl-3.0
- Created: 2022-09-03T23:56:54.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2022-09-03T23:56:55.000Z (about 2 years ago)
- Last Synced: 2023-03-06T01:36:23.392Z (over 1 year ago)
- Size: 13.7 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0