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https://github.com/carloscraveiro/riscv_based_processor
A RISC-V based Processor written in Verilog for the course SEL0628
https://github.com/carloscraveiro/riscv_based_processor
Last synced: 2 days ago
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A RISC-V based Processor written in Verilog for the course SEL0628
- Host: GitHub
- URL: https://github.com/carloscraveiro/riscv_based_processor
- Owner: CarlosCraveiro
- License: gpl-3.0
- Created: 2022-10-10T16:29:44.000Z (about 2 years ago)
- Default Branch: main
- Last Pushed: 2023-01-10T21:47:00.000Z (almost 2 years ago)
- Last Synced: 2023-06-30T14:40:01.488Z (over 1 year ago)
- Language: VHDL
- Size: 14.2 MB
- Stars: 6
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
- License: LICENSE
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README
# RISCV_based_processor
A RISC-V based Processor written in Verilog for the course SEL0628
More details about the project can be found in our Wiki!