https://github.com/catkira/complex_multiplier
HDL code for a complex multiplier with AXI stream Interface
https://github.com/catkira/complex_multiplier
axis fpga hdl verilog
Last synced: about 1 year ago
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HDL code for a complex multiplier with AXI stream Interface
- Host: GitHub
- URL: https://github.com/catkira/complex_multiplier
- Owner: catkira
- Created: 2020-12-30T19:40:12.000Z (over 5 years ago)
- Default Branch: master
- Last Pushed: 2023-04-06T13:08:20.000Z (about 3 years ago)
- Last Synced: 2025-03-29T20:43:56.164Z (about 1 year ago)
- Topics: axis, fpga, hdl, verilog
- Language: Python
- Homepage:
- Size: 61.5 KB
- Stars: 13
- Watchers: 3
- Forks: 2
- Open Issues: 0