https://github.com/catkira/complex_multiplier

HDL code for a complex multiplier with AXI stream Interface
https://github.com/catkira/complex_multiplier

axis fpga hdl verilog

Last synced: about 2 months ago
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HDL code for a complex multiplier with AXI stream Interface

• Host: GitHub
• URL: https://github.com/catkira/complex_multiplier
• Owner: catkira
• Created: 2020-12-30T19:40:12.000Z (almost 4 years ago)
• Default Branch: master
• Last Pushed: 2023-02-21T10:43:48.000Z (almost 2 years ago)
• Last Synced: 2023-03-03T09:54:05.237Z (almost 2 years ago)
• Topics: axis, fpga, hdl, verilog
• Language: Python
• Homepage:
• Size: 75.2 KB
• Stars: 7
• Watchers: 2
• Forks: 0
• Open Issues: 0

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