https://github.com/ccelio/riscv-pythia

A RISC-V superscalar front-end simulator.
https://github.com/ccelio/riscv-pythia

Last synced: about 2 months ago
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A RISC-V superscalar front-end simulator.

• Host: GitHub
• URL: https://github.com/ccelio/riscv-pythia
• Owner: ccelio
• Created: 2014-09-07T02:44:14.000Z (over 10 years ago)
• Default Branch: master
• Last Pushed: 2014-09-12T22:06:45.000Z (over 10 years ago)
• Last Synced: 2024-10-10T20:45:40.562Z (2 months ago)
• Language: Python
• Size: 2.22 MB
• Stars: 5
• Watchers: 3
• Forks: 4
• Open Issues: 0
• Metadata Files:
  • Readme: README.md

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README

        
*Christopher Celio*

2014 Sep 1

This is a trace-based simulator designed to explore branch prediction

strategies. 

In particular, BTB, BHT, and RAS interations with superscalar fetch units.

Getting Started

---------------

*replay mode*

    ./pythia -t vvadd

*live mode*

    

    ./pythia -s ../riscv-tools/riscv-tests/benchmarks/vvadd.riscv

Live mode assumes "lspike" is installed.

For more information:

    ./pythia -h

There are *two* modes - "live" mode and "replay" mode.

*"Live" mode* - is the default mode that invokes "lspike" and pipes the commit

log to Pythia. use "-s" to specify the benchmark and its arguments. 

*"Replay" mode* - use "-t" to name a tracefile in the "traces" directory to replay a run.

Setting Up

----------

"Live" mode will require the [riscv-tools](https://github.com/ucb-bar/riscv-tools) 

to be installed. In particular, it needs to make use of the "commit logging"

ability of "spike".

1. Modify riscv-tool's "build.sh" to compile the "spike" ISA simulator into a new directory.

```

build_project riscv-fesvr --prefix=$RISCV/logger

build_project riscv-isa-sim --prefix=$RISCV/logger --with-fesvr=$RISCV/logger --enable-commitlog 

```

2. Rename $RISCV/logger/bin/spike to $RISCV/logger/bin/lspike. 

3. Finally, add $RISCV/logger/bin to your bash environment path.