https://github.com/cdelmoral/logic-simulator
Compiler and simulator for digital logic
https://github.com/cdelmoral/logic-simulator
Last synced: 3 months ago
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Compiler and simulator for digital logic
- Host: GitHub
- URL: https://github.com/cdelmoral/logic-simulator
- Owner: cdelmoral
- Created: 2013-11-04T04:27:24.000Z (over 11 years ago)
- Default Branch: master
- Last Pushed: 2015-01-27T02:29:32.000Z (over 10 years ago)
- Last Synced: 2025-01-18T08:24:12.523Z (5 months ago)
- Language: Java
- Size: 1.09 MB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0
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Metadata Files:
- Readme: README.md
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README
# Digital logic compiler and simulator
Computer simulator and compiler for digital logic, which is described in a simplification of Verilog.
### How to use it ###
If you have you own pseudo-Verilog files you can process them by first storing the files containing the hardware description and the input stimuli (if any) in the `test_cases/` folder and passing the name of the description to `com.logicsimulator.MainProgram`. This will generate the file `.tokens`, `.netlist`, `.syntax` and `.sim_out`. The first three generated files are mostly for debugging purposes, they are just a representation of the architecture created by the program to process and simulate the hardware description and behavior. The last one `sim_out` contains the output generated by the circuit.
The `golden.*` files contain the verified output of the set of files for testing purposes.