Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1
computer-architecture pipeline risc-v rv32im verilog
Last synced: 2 days ago
JSON representation
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave was used to observe the behavior.
- Host: GitHub
- URL: https://github.com/cepdnaclk/e16-co502-rv32im-pipeline-implementation-group1
- Owner: cepdnaclk
- Created: 2021-06-30T16:54:58.000Z (over 3 years ago)
- Default Branch: forwarding
- Last Pushed: 2021-10-31T14:42:19.000Z (about 3 years ago)
- Last Synced: 2023-03-05T05:08:26.384Z (over 1 year ago)
- Topics: computer-architecture, pipeline, risc-v, rv32im, verilog
- Language: Verilog
- Homepage: https://cepdnaclk.github.io/e16-co502-RV32IM-pipeline-implementation-group1/
- Size: 8.34 MB
- Stars: 3
- Watchers: 4
- Forks: 3
- Open Issues: 0