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https://github.com/cgkantidis/gen_design
Generate a verilog file and an acompanying SPEF file, for a hierarchical design
https://github.com/cgkantidis/gen_design
cpp cpp20 eda
Last synced: 8 days ago
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Generate a verilog file and an acompanying SPEF file, for a hierarchical design
- Host: GitHub
- URL: https://github.com/cgkantidis/gen_design
- Owner: cgkantidis
- License: mit
- Created: 2024-10-11T13:32:56.000Z (4 months ago)
- Default Branch: main
- Last Pushed: 2024-11-07T13:56:18.000Z (3 months ago)
- Last Synced: 2024-11-25T16:14:27.108Z (2 months ago)
- Topics: cpp, cpp20, eda
- Language: C++
- Homepage:
- Size: 38.1 KB
- Stars: 0
- Watchers: 1
- Forks: 0
- Open Issues: 0
-
Metadata Files:
- Readme: README.md
- License: LICENSE.md
Awesome Lists containing this project
README
# Build
## Writing uncompressed files
```bash
cmake -S . -B build -DCMAKE_BUILD_TYPE=Release
cmake --build build -j$(nproc)
```
## Writing compressed files (slower but takes less disk space)
```bash
cmake -S . -B build -DCMAKE_BUILD_TYPE=Release -DWRITE_COMPRESSED=ON
cmake --build build -j$(nproc)
```
# Run
## Getting Help
```bash
build/gen_design --help
# Generate the necessary verilog and SPEF files for a design
# Usage:
# gen_design [OPTION...]
#
# -n, --num_nets arg The number of nets in each block hierarchy
# -b, --num_blocks arg The number of block hierarchies in the top
# hierarchy
# -h, --help Print this help message
```
## Generating design files
To generate a design with 4.5B nets
```bash
build/gen_design -n 1000000 -b 4500
```