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https://github.com/charkster/adc_block_ram_spi_top
Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
https://github.com/charkster/adc_block_ram_spi_top
block-ram cmod-a7 fpga pll raspberry-pi spi xadc
Last synced: about 21 hours ago
JSON representation
Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
- Host: GitHub
- URL: https://github.com/charkster/adc_block_ram_spi_top
- Owner: charkster
- License: mit
- Created: 2021-07-16T06:28:08.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-10-22T23:28:10.000Z (about 2 years ago)
- Last Synced: 2023-04-29T22:59:04.572Z (over 1 year ago)
- Topics: block-ram, cmod-a7, fpga, pll, raspberry-pi, spi, xadc
- Language: SystemVerilog
- Homepage:
- Size: 212 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0