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https://github.com/charkster/trigger
SystemVerilog FPGA design of a custom trigger circuit which can be used with oscilloscopes or logic analyzers.
https://github.com/charkster/trigger
cmod-a7 fpga scarf systemverilog trigger
Last synced: about 24 hours ago
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SystemVerilog FPGA design of a custom trigger circuit which can be used with oscilloscopes or logic analyzers.
- Host: GitHub
- URL: https://github.com/charkster/trigger
- Owner: charkster
- License: mit
- Created: 2021-05-09T22:14:45.000Z (over 3 years ago)
- Default Branch: main
- Last Pushed: 2022-10-22T23:34:47.000Z (about 2 years ago)
- Last Synced: 2023-04-29T22:59:05.247Z (over 1 year ago)
- Topics: cmod-a7, fpga, scarf, systemverilog, trigger
- Language: SystemVerilog
- Homepage:
- Size: 313 KB
- Stars: 0
- Watchers: 2
- Forks: 0
- Open Issues: 0