https://github.com/cheyao/achieve-core

RISC-V SoC + OS
https://github.com/cheyao/achieve-core

core risc-v soc verilog

Last synced: 19 days ago
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RISC-V SoC + OS

• Host: GitHub
• URL: https://github.com/cheyao/achieve-core
• Owner: cheyao
• Created: 2023-01-01T18:22:29.000Z (about 2 years ago)
• Default Branch: main
• Last Pushed: 2023-02-26T16:10:58.000Z (almost 2 years ago)
• Last Synced: 2024-11-09T13:14:16.391Z (2 months ago)
• Topics: core, risc-v, soc, verilog
• Language: SystemVerilog
• Homepage:
• Size: 12.4 MB
• Stars: 3
• Watchers: 1
• Forks: 0
• Open Issues: 0

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