https://github.com/chili-chips-ba/openeye-camsi
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
https://github.com/chili-chips-ba/openeye-camsi
camera csi ddr fpga hd hdmi image-sensor imx283 isp low-budget opensource raspberrypi rtl serdes signal-integrity systemverilog uhd video vlc
Last synced: 15 days ago
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A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
- Host: GitHub
- URL: https://github.com/chili-chips-ba/openeye-camsi
- Owner: chili-chips-ba
- License: bsd-3-clause
- Created: 2023-12-12T00:48:54.000Z (over 1 year ago)
- Default Branch: main
- Last Pushed: 2025-04-24T22:46:38.000Z (27 days ago)
- Last Synced: 2025-05-01T21:11:48.054Z (20 days ago)
- Topics: camera, csi, ddr, fpga, hd, hdmi, image-sensor, imx283, isp, low-budget, opensource, raspberrypi, rtl, serdes, signal-integrity, systemverilog, uhd, video, vlc
- Language: SystemVerilog
- Homepage: https://nlnet.nl/project/TISG
- Size: 276 MB
- Stars: 47
- Watchers: 16
- Forks: 10
- Open Issues: 1
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Metadata Files:
- Readme: README.md
- License: LICENSE