https://github.com/chipfoundry/openframe_user_project
https://github.com/chipfoundry/openframe_user_project
Last synced: 18 days ago
JSON representation
- Host: GitHub
- URL: https://github.com/chipfoundry/openframe_user_project
- Owner: chipfoundry
- License: apache-2.0
- Created: 2025-04-29T16:59:35.000Z (about 1 year ago)
- Default Branch: main
- Last Pushed: 2026-02-09T11:56:30.000Z (5 months ago)
- Last Synced: 2026-02-09T16:37:57.588Z (5 months ago)
- Language: Verilog
- Size: 29.9 MB
- Stars: 8
- Watchers: 1
- Forks: 4
- Open Issues: 1
-
Metadata Files:
- Readme: README.md
- License: LICENSE
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## Table of Contents
- [Overview](#overview)
- [Documentation & Resources](#documentation--resources)
- [Prerequisites](#prerequisites)
- [Project Structure](#project-structure)
- [Starting Your Project](#starting-your-project)
- [Development Flow](#development-flow)
- [Local Precheck](#local-precheck)
- [Checklist for Shuttle Submission](#checklist-for-shuttle-submission)
## Overview
OpenFrame is a ChipFoundry project template that provides only a bare padframe (no integrated SoC), giving you a 15 mm² user area and 44 GPIOs to design your own custom chip. You are free to implement your design and directly connect it to the available GPIOs throught the pins provided on the openframe wrapper.
---
## Documentation & Resources
For detailed hardware specifications and design guidelines, refer to the following official documents:
* **[ChipFoundry Marketplace](https://platform.chipfoundry.io/marketplace)**: Access additional IP blocks, EDA tools, and shuttle services.
---
## Prerequisites
Ensure your environment meets the following requirements:
1. **Docker** [Linux](https://docs.docker.com/desktop/setup/install/linux/ubuntu/) | [Windows](https://docs.docker.com/desktop/setup/install/windows-install/) | [Mac](https://docs.docker.com/desktop/setup/install/mac-install/)
2. **Python 3.8+** with `pip`.
3. **Git**: For repository management.
---
## Project Structure
A successful OpenFrame project requires a specific directory layout for the automated tools to function:
| Directory | Description |
| :--- | :--- |
| `openlane/` | Configuration files for hardening macros and the wrapper. |
| `verilog/rtl/` | Source Verilog code for the project. |
| `verilog/gl/` | Gate-level netlists (generated after hardening). |
| `verilog/dv/` | Design Verification (cocotb and Verilog testbenches). |
| `gds/` | Final GDSII binary files for fabrication. |
| `lef/` | Library Exchange Format files for the macros. |
---
## Starting Your Project
### 1. Repository Setup
Create a new repository based on the `openframe_user_project` template and clone it to your local machine:
```bash
git clone
pip install chipfoundry-cli
cd
```
### 2. Project Initialization
> [!IMPORTANT]
> Run this first! Initialize your project configuration:
```bash
cf init
```
This creates `.cf/project.json` with project metadata. **This must be run before any other commands**
### 3. Environment Setup
Install the ChipFoundry CLI tool and set up the local environment (PDKs, OpenLane, and OpenFrame):
```bash
cf setup
```
The `cf setup` command installs:
- OpenFrame: The OpenFrame harness template.
- OpenLane: The RTL-to-GDS hardening flow.
- PDK: Skywater 130nm process design kit.
- Timing Scripts: For Static Timing Analysis (STA).
---
## Development Flow
### Hardening the Design
Hardening is the process of synthesizing your RTL and performing Place & Route (P&R) to create a GDSII layout.
#### Macro Hardening
Create a subdirectory for each custom macro under `openlane/` containing your `config.json`.
```bash
cf harden --list # List detected configurations
cf harden # Harden a specific macro
```
#### Integration
Instantiate your module(s) in `verilog/rtl/openframe_project_wrapper.v`.
Update `openlane/openframe_project_wrapper/config.json` environment variables (`VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS`, `EXTRA_GDS_FILES`) to point to your new macros.
#### Wrapper Hardening
Finalize the top-level user project:
```bash
cf harden openframe_project_wrapper
```
### Important Notes
**Connecting to Power:**
- Ensure your design is connected to power using the power pins on the wrapper.
- Use the `vccd1_connection` and `vssd1_connection` macros, which contain the necessary vias and nets for power connections.
### Verification
#### 1. Simulation
We use cocotb for functional verification. Ensure your file lists are updated in `verilog/includes/`.
Run RTL Simulation:
```bash
cf verify
```
Run Gate-Level (GL) Simulation:
```bash
cf verify --sim gl
```
Run all tests:
```bash
cf verify --all
```
---
## Local Precheck
Before submitting your design for fabrication, run the local precheck to ensure it complies with all shuttle requirements:
```bash
cf precheck
```
You can also run specific checks or disable LVS:
```bash
cf precheck --disable-lvs # Skip LVS check
cf precheck --checks license --checks makefile # Run specific checks only
```
---
## Checklist for Shuttle Submission
- [ ] Top-level macro is named openframe_project_wrapper.
- [ ] Full Chip Simulation passes for both RTL and GL.
- [ ] Hardened Macros are LVS and DRC clean.
- [ ] openframe_project_wrapper matches the required pin order/template.
- [ ] Design is properly connected to power (vccd1/vssd1).
- [ ] Design passes the local cf precheck.
- [ ] Documentation (this README) is updated with project-specific details.