https://github.com/chipsalliance/Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
https://github.com/chipsalliance/Surelog

antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard

Last synced: 2 months ago
JSON representation

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

• Host: GitHub
• URL: https://github.com/chipsalliance/Surelog
• Owner: chipsalliance
• License: apache-2.0
• Created: 2019-10-30T01:25:50.000Z (about 5 years ago)
• Default Branch: master
• Last Pushed: 2024-10-07T01:37:24.000Z (4 months ago)
• Last Synced: 2024-11-05T21:48:52.220Z (3 months ago)
• Topics: antlr, antlr4-grammar, elaboration, linter, parser, parser-ast, preprocessor, python-api, systemverilog, uvm, verilog, vpi, vpi-api, vpi-standard
• Language: C++
• Homepage:
• Size: 832 MB
• Stars: 362
• Watchers: 26
• Forks: 69
• Open Issues: 51
• Metadata Files:
  • Readme: README.md
  • License: LICENSE

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